This invention relates to a semiconductor device using a silicon nitride film or silicon oxide film containing nitrogen as a gate insulating film and a method for manufacturing the same.
In order to enhance the performance of a semiconductor integrated circuit including MIS semiconductor elements and lower the cost thereof, it is important to miniaturize the elements and increase the integration density. Miniaturization of the elements is effected according to the design rule.
Further, in order to increase the integration density of the elements, it is important to not only reduce the size of the elements but also reduce the size of the element isolating region. As the effective technique for miniaturizing the size of the element isolating region, a trench type element isolation (STI:Shallow Trench Isolation) technique is known.
When a MOS transistor using a polysilicon film containing boron as a gate electrode is miniaturized, it is necessary to use a nitrided silicon oxide film (which is a silicon oxide film containing nitrogen) as a gate insulating film in order to prevent boron from being diffused into the silicon substrate. It is necessary to simultaneously supply an oxidizing agent and nitriding agent in order to form a thinner nitrided silicon oxide film.
Next, a method for manufacturing the MOS transistor using the above gate insulating film (nitrided silicon oxide film) is explained with reference to FIGS. 9A to 9H. These figures show cross sections of the MOS transistor taken along a line passing across the gate electrode and set in parallel to the gate length direction.
First, as shown in FIG. 9A, a silicon oxide film 82 with a thickness of 10 nm is formed on the (100) surface of a silicon substrate 81 by use of a thermal oxidation method. Then, as shown in FIG. 9A, a silicon nitride film 83 with a thickness of 200 nm is formed on the silicon oxide film 82 by use of the LPCVD method.
Next, as shown in FIG. 9B, trench type shallow element isolation grooves 84 are formed in the surface of the silicon substrate 81 by sequentially etching the silicon nitride film 83, silicon oxide film 82 and silicon substrate 81.
In more detail, a photoresist pattern (not shown) which defines an element forming region (active area) is formed on the silicon nitride film 83 and the pattern of the photoresist pattern is transferred onto the silicon nitride film 83 by etching the silicon nitride film 83 by use of an RIE method with the photoresist pattern used as a mask.
Next, after the photoresist pattern is removed, the element isolation grooves 84 are formed by sequentially etching the silicon oxide film 82 and the silicon substrate 81 by use of the RIE method with the silicon nitride film 83 used as a mask.
After this, as shown in FIG. 9C, a silicon oxide film 85 with a thickness of 15 nm is formed on the exposed surface of the silicon substrate 81 by use of a thermal oxidation method.
Next, as shown in FIG. 9D, an element isolation insulating film 86 is filled in the internal portions of grooves formed by the element isolation grooves 84 as well as the silicon nitride film 83 and silicon oxide film 82 lying thereon, and then the surface of the structure is made flat.
In more detail, a silicon oxide film used as the element isolation insulating film 86 is formed on the entire surface by use of the LPCVD method so as to fill the grooves formed of the element isolation grooves 84 and the silicon nitride film 83 lying thereon, then the silicon film is polished by use of the CMP method until the surface of the silicon nitride film 83 is exposed. As a result, the structure as shown in FIG. 9D is obtained.
Next, as shown in FIG. 9E, the element isolation insulating film (silicon oxide film) 86 is retreated to substantially the surface portion of the silicon substrate 81 by use of an ammonium fluoride solution and the silicon nitride film 83 is removed by use of a hot phosphoric acid, then the silicon oxide film 82 is removed by use of a dilute hydrofluoric acid to expose the surface of the silicon substrate 81 (active area) in the element forming region.
Next, for example, as shown in FIG. 9F, an oxidizing-nitriding process is effected at 850.degree. C. by use of dinitrogen monoxide gas, to form a nitrided silicon oxide film (gate insulating film) 87 with a thickness of 4 nm on the exposed surface of the silicon substrate 81 and then an amorphous silicon film 88 with a thickness of 100 nm, which contains boron as impurity with high impurity concentration and which will be used as a gate electrode, is formed by use of the LPCVD method.
After this, like a conventional MOS transistor manufacturing method, the processes for patterning the gate electrode, for forming source and drain diffusion layers and for forming wirings are effected to complete a MOS transistor.
However, this type of MOS transistor manufacturing method has the following problem.
As shown in FIG. 9G, the portion of the nitrided silicon oxide film (gate insulating film) 87 lying on the upper-end corner portion of the side wall of the element isolation groove 84 is not so thick as the portion of the same lying on the element forming region. Therefore, the breakdown voltage of the nitrided silicon oxide film (gate insulating film) 87 on the upper-end corner portion of the side wall of the element isolation groove 84 in which the electric field is concentrated becomes low and thus the reliability is lowered.
Further, in the thermal oxidation method, which is a conventional method for forming a normal gate insulating film, the oxidation rate varies on the (100) face and the (110) face which correspond to the side wall surface of the element isolating groove 84, (the rate on the (110) face is about 1.5 times greater than that on the (100) face) and therefore, as shown in FIG. 9H, the film thickness of the thermal silicon oxide film (gate insulating film) 87 at the upper-end corner portion of the side wall of the element isolation groove 84 is greater than the film thickness of the thermal silicon oxide film (gate insulating film) 87 in the element forming region. A high breakdown voltage of the thermal silicon oxide film (gate insulating film) 87 is therefore attained and thus there have been no problems regarding a low reliability due to a low gate breakdown voltage. However, if a dinitrogen monoxide gas is employed, both oxidation and nitration may occur, and thus the difference of oxidation rate on the (100) face and the (110) face may be reduced.
In order to solve the problem of a lowering in the breakdown voltage of the nitrided silicon oxide film (gate insulating film) 87, a portion of the nitrided silicon oxide film (gate insulating film) 87 at the above-mentioned corner portion, that is, a portion lying between the upper-end corner portion of the side wall of the element isolation groove 84 and the end portion of the element forming region formed in contact therewith may be made thicker than a portion of the nitrided silicon oxide film (gate insulating film) 87 which lies on the central flat portion of the element forming region.
Such a technique for forming a gate insulating film having different film thickness on different regions of the substrate is known in the prior art (refer to Japanese Patent Application No. 3-249810).
However, if this type of conventional technique is used, it will be necessary to use the photolithography in order to mask the corner portion, and therefore, additional steps (additional time for effecting the steps) and additional manufacturing costs will be necessary.
Further, a problem of misalignment may occur and it is therefore difficult to form a thick gate insulating film on the corner portion without fault.
As described above, in a MOS transistor using the nitrided silicon oxide film as the gate insulating film, it has been considered that a nitrided silicon oxide film is formed so as to have a thin part on the central flat portion of the element forming region as designed and a thick part on the corner portion, to prevent a lowering in the breakdown voltage of the gate insulating film in the corner portion.
However, such a conventional method for forming the gate insulating film having different film thickness on the different regions of the substrate requires the photolithography.
Therefore, there occur problems that additional steps (additional time for effecting the steps) as well as additional manufacturing costs will be needed and it is difficult to form a thick gate insulating film on the corner portion without fault, due to misalignment.